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<a href="#define-members">Macros</a> &#124;
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<div class="title">xiicps_hw.h File Reference</div>  </div>
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Macros</h2></td></tr>
<tr class="memitem:gabcc20fce80c1e8dff27be4e584c2cc27"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__v3__0.html#gabcc20fce80c1e8dff27be4e584c2cc27">XIicPs_ReadReg</a>(BaseAddress,  RegOffset)&#160;&#160;&#160;XIicPs_In32((BaseAddress) + (u32)(RegOffset))</td></tr>
<tr class="memdesc:gabcc20fce80c1e8dff27be4e584c2cc27"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read an IIC register.  <a href="group__iicps__v3__0.html#gabcc20fce80c1e8dff27be4e584c2cc27">More...</a><br /></td></tr>
<tr class="separator:gabcc20fce80c1e8dff27be4e584c2cc27"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa0bde6894589023ea8248a9d9cdc73c5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__v3__0.html#gaa0bde6894589023ea8248a9d9cdc73c5">XIicPs_WriteReg</a>(BaseAddress,  RegOffset,  RegisterValue)&#160;&#160;&#160;XIicPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue))</td></tr>
<tr class="memdesc:gaa0bde6894589023ea8248a9d9cdc73c5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write an IIC register.  <a href="group__iicps__v3__0.html#gaa0bde6894589023ea8248a9d9cdc73c5">More...</a><br /></td></tr>
<tr class="separator:gaa0bde6894589023ea8248a9d9cdc73c5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab8f0f78d7389924d17d2b7b49f622cf1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__v3__0.html#gab8f0f78d7389924d17d2b7b49f622cf1">XIicPs_ReadIER</a>(BaseAddress)&#160;&#160;&#160;<a class="el" href="group__iicps__v3__0.html#gabcc20fce80c1e8dff27be4e584c2cc27">XIicPs_ReadReg</a>((BaseAddress),  <a class="el" href="group__iicps__v3__0.html#ga471cbaf2444941e33de173ea5e5c7f03">XIICPS_IER_OFFSET</a>)</td></tr>
<tr class="memdesc:gab8f0f78d7389924d17d2b7b49f622cf1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read the interrupt enable register.  <a href="group__iicps__v3__0.html#gab8f0f78d7389924d17d2b7b49f622cf1">More...</a><br /></td></tr>
<tr class="separator:gab8f0f78d7389924d17d2b7b49f622cf1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf7a3f4b57fe275f426ac9b771b187b23"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__v3__0.html#gaf7a3f4b57fe275f426ac9b771b187b23">XIicPs_EnableInterrupts</a>(BaseAddress,  IntrMask)&#160;&#160;&#160;<a class="el" href="group__iicps__v3__0.html#gaa0bde6894589023ea8248a9d9cdc73c5">XIicPs_WriteReg</a>((BaseAddress), <a class="el" href="group__iicps__v3__0.html#ga471cbaf2444941e33de173ea5e5c7f03">XIICPS_IER_OFFSET</a>, (IntrMask))</td></tr>
<tr class="memdesc:gaf7a3f4b57fe275f426ac9b771b187b23"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write to the interrupt enable register.  <a href="group__iicps__v3__0.html#gaf7a3f4b57fe275f426ac9b771b187b23">More...</a><br /></td></tr>
<tr class="separator:gaf7a3f4b57fe275f426ac9b771b187b23"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga90efda2a784d4b972f1835b0ba81cde1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__v3__0.html#ga90efda2a784d4b972f1835b0ba81cde1">XIicPs_DisableAllInterrupts</a>(BaseAddress)</td></tr>
<tr class="memdesc:ga90efda2a784d4b972f1835b0ba81cde1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable all interrupts.  <a href="group__iicps__v3__0.html#ga90efda2a784d4b972f1835b0ba81cde1">More...</a><br /></td></tr>
<tr class="separator:ga90efda2a784d4b972f1835b0ba81cde1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6a21536b3361fa36f00745a3e653fbbd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__v3__0.html#ga6a21536b3361fa36f00745a3e653fbbd">XIicPs_DisableInterrupts</a>(BaseAddress,  IntrMask)</td></tr>
<tr class="memdesc:ga6a21536b3361fa36f00745a3e653fbbd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable selected interrupts.  <a href="group__iicps__v3__0.html#ga6a21536b3361fa36f00745a3e653fbbd">More...</a><br /></td></tr>
<tr class="separator:ga6a21536b3361fa36f00745a3e653fbbd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Register Map</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Register offsets for the IIC. </p>
</div></td></tr>
<tr class="memitem:ga0c96ab97015c857822df599608ba9c10"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__v3__0.html#ga0c96ab97015c857822df599608ba9c10">XIICPS_CR_OFFSET</a>&#160;&#160;&#160;0x00U</td></tr>
<tr class="memdesc:ga0c96ab97015c857822df599608ba9c10"><td class="mdescLeft">&#160;</td><td class="mdescRight">32-bit Control  <a href="group__iicps__v3__0.html#ga0c96ab97015c857822df599608ba9c10">More...</a><br /></td></tr>
<tr class="separator:ga0c96ab97015c857822df599608ba9c10"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga12b4d0ee4dce6172ba78a0dec5666a72"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__v3__0.html#ga12b4d0ee4dce6172ba78a0dec5666a72">XIICPS_SR_OFFSET</a>&#160;&#160;&#160;0x04U</td></tr>
<tr class="memdesc:ga12b4d0ee4dce6172ba78a0dec5666a72"><td class="mdescLeft">&#160;</td><td class="mdescRight">Status.  <a href="group__iicps__v3__0.html#ga12b4d0ee4dce6172ba78a0dec5666a72">More...</a><br /></td></tr>
<tr class="separator:ga12b4d0ee4dce6172ba78a0dec5666a72"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3d97551edd7013b07093cac16dbe80f1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__v3__0.html#ga3d97551edd7013b07093cac16dbe80f1">XIICPS_ADDR_OFFSET</a>&#160;&#160;&#160;0x08U</td></tr>
<tr class="memdesc:ga3d97551edd7013b07093cac16dbe80f1"><td class="mdescLeft">&#160;</td><td class="mdescRight">IIC Address.  <a href="group__iicps__v3__0.html#ga3d97551edd7013b07093cac16dbe80f1">More...</a><br /></td></tr>
<tr class="separator:ga3d97551edd7013b07093cac16dbe80f1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac9101ca416d8b9e303b4a65c4840a1d5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__v3__0.html#gac9101ca416d8b9e303b4a65c4840a1d5">XIICPS_DATA_OFFSET</a>&#160;&#160;&#160;0x0CU</td></tr>
<tr class="memdesc:gac9101ca416d8b9e303b4a65c4840a1d5"><td class="mdescLeft">&#160;</td><td class="mdescRight">IIC FIFO Data.  <a href="group__iicps__v3__0.html#gac9101ca416d8b9e303b4a65c4840a1d5">More...</a><br /></td></tr>
<tr class="separator:gac9101ca416d8b9e303b4a65c4840a1d5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9ec604e5ed330606d24a082484e905f0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__v3__0.html#ga9ec604e5ed330606d24a082484e905f0">XIICPS_ISR_OFFSET</a>&#160;&#160;&#160;0x10U</td></tr>
<tr class="memdesc:ga9ec604e5ed330606d24a082484e905f0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Status.  <a href="group__iicps__v3__0.html#ga9ec604e5ed330606d24a082484e905f0">More...</a><br /></td></tr>
<tr class="separator:ga9ec604e5ed330606d24a082484e905f0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2afdc061285f0155f3fbbf322beae54f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__v3__0.html#ga2afdc061285f0155f3fbbf322beae54f">XIICPS_TRANS_SIZE_OFFSET</a>&#160;&#160;&#160;0x14U</td></tr>
<tr class="memdesc:ga2afdc061285f0155f3fbbf322beae54f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transfer Size.  <a href="group__iicps__v3__0.html#ga2afdc061285f0155f3fbbf322beae54f">More...</a><br /></td></tr>
<tr class="separator:ga2afdc061285f0155f3fbbf322beae54f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3750481db8ebadadea48985f0abcb755"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__v3__0.html#ga3750481db8ebadadea48985f0abcb755">XIICPS_SLV_PAUSE_OFFSET</a>&#160;&#160;&#160;0x18U</td></tr>
<tr class="memdesc:ga3750481db8ebadadea48985f0abcb755"><td class="mdescLeft">&#160;</td><td class="mdescRight">Slave monitor pause.  <a href="group__iicps__v3__0.html#ga3750481db8ebadadea48985f0abcb755">More...</a><br /></td></tr>
<tr class="separator:ga3750481db8ebadadea48985f0abcb755"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga61f5015241d07352f5cad00c589ec4e0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__v3__0.html#ga61f5015241d07352f5cad00c589ec4e0">XIICPS_TIME_OUT_OFFSET</a>&#160;&#160;&#160;0x1CU</td></tr>
<tr class="memdesc:ga61f5015241d07352f5cad00c589ec4e0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Time Out.  <a href="group__iicps__v3__0.html#ga61f5015241d07352f5cad00c589ec4e0">More...</a><br /></td></tr>
<tr class="separator:ga61f5015241d07352f5cad00c589ec4e0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0668ec3389dd427fecfca4d1b9d2f0c4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__v3__0.html#ga0668ec3389dd427fecfca4d1b9d2f0c4">XIICPS_IMR_OFFSET</a>&#160;&#160;&#160;0x20U</td></tr>
<tr class="memdesc:ga0668ec3389dd427fecfca4d1b9d2f0c4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Enabled Mask.  <a href="group__iicps__v3__0.html#ga0668ec3389dd427fecfca4d1b9d2f0c4">More...</a><br /></td></tr>
<tr class="separator:ga0668ec3389dd427fecfca4d1b9d2f0c4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga471cbaf2444941e33de173ea5e5c7f03"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__v3__0.html#ga471cbaf2444941e33de173ea5e5c7f03">XIICPS_IER_OFFSET</a>&#160;&#160;&#160;0x24U</td></tr>
<tr class="memdesc:ga471cbaf2444941e33de173ea5e5c7f03"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Enable.  <a href="group__iicps__v3__0.html#ga471cbaf2444941e33de173ea5e5c7f03">More...</a><br /></td></tr>
<tr class="separator:ga471cbaf2444941e33de173ea5e5c7f03"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac95b4e2bd04257b322e5bf66f956bdf3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__v3__0.html#gac95b4e2bd04257b322e5bf66f956bdf3">XIICPS_IDR_OFFSET</a>&#160;&#160;&#160;0x28U</td></tr>
<tr class="memdesc:gac95b4e2bd04257b322e5bf66f956bdf3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Disable.  <a href="group__iicps__v3__0.html#gac95b4e2bd04257b322e5bf66f956bdf3">More...</a><br /></td></tr>
<tr class="separator:gac95b4e2bd04257b322e5bf66f956bdf3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Control Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains various control bits that affects the operation of the IIC controller.</p>
<p>Read/Write. </p>
</div></td></tr>
<tr class="memitem:gae1eb58bcf8d77fd6a8f9325d5344b390"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__v3__0.html#gae1eb58bcf8d77fd6a8f9325d5344b390">XIICPS_CR_DIV_A_MASK</a>&#160;&#160;&#160;0x0000C000U</td></tr>
<tr class="memdesc:gae1eb58bcf8d77fd6a8f9325d5344b390"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clock Divisor A.  <a href="group__iicps__v3__0.html#gae1eb58bcf8d77fd6a8f9325d5344b390">More...</a><br /></td></tr>
<tr class="separator:gae1eb58bcf8d77fd6a8f9325d5344b390"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae980b732a8b41e97461d097cdca82d38"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__v3__0.html#gae980b732a8b41e97461d097cdca82d38">XIICPS_CR_DIV_A_SHIFT</a>&#160;&#160;&#160;14U</td></tr>
<tr class="memdesc:gae980b732a8b41e97461d097cdca82d38"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clock Divisor A shift.  <a href="group__iicps__v3__0.html#gae980b732a8b41e97461d097cdca82d38">More...</a><br /></td></tr>
<tr class="separator:gae980b732a8b41e97461d097cdca82d38"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab87d93689afe5c24a5619083ea1f3ca9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__v3__0.html#gab87d93689afe5c24a5619083ea1f3ca9">XIICPS_DIV_A_MAX</a>&#160;&#160;&#160;4U</td></tr>
<tr class="memdesc:gab87d93689afe5c24a5619083ea1f3ca9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Maximum value of Divisor A.  <a href="group__iicps__v3__0.html#gab87d93689afe5c24a5619083ea1f3ca9">More...</a><br /></td></tr>
<tr class="separator:gab87d93689afe5c24a5619083ea1f3ca9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaee06a0e2ceece45ef3ca15fffacbaac3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__v3__0.html#gaee06a0e2ceece45ef3ca15fffacbaac3">XIICPS_CR_DIV_B_MASK</a>&#160;&#160;&#160;0x00003F00U</td></tr>
<tr class="memdesc:gaee06a0e2ceece45ef3ca15fffacbaac3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clock Divisor B.  <a href="group__iicps__v3__0.html#gaee06a0e2ceece45ef3ca15fffacbaac3">More...</a><br /></td></tr>
<tr class="separator:gaee06a0e2ceece45ef3ca15fffacbaac3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0475ff513956035cd712dd4ee3301364"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__v3__0.html#ga0475ff513956035cd712dd4ee3301364">XIICPS_CR_DIV_B_SHIFT</a>&#160;&#160;&#160;8U</td></tr>
<tr class="memdesc:ga0475ff513956035cd712dd4ee3301364"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clock Divisor B shift.  <a href="group__iicps__v3__0.html#ga0475ff513956035cd712dd4ee3301364">More...</a><br /></td></tr>
<tr class="separator:ga0475ff513956035cd712dd4ee3301364"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga167d2a48ba5ab4cdf58f229bf6a0b554"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__v3__0.html#ga167d2a48ba5ab4cdf58f229bf6a0b554">XIICPS_CR_CLR_FIFO_MASK</a>&#160;&#160;&#160;0x00000040U</td></tr>
<tr class="memdesc:ga167d2a48ba5ab4cdf58f229bf6a0b554"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clear FIFO, auto clears.  <a href="group__iicps__v3__0.html#ga167d2a48ba5ab4cdf58f229bf6a0b554">More...</a><br /></td></tr>
<tr class="separator:ga167d2a48ba5ab4cdf58f229bf6a0b554"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gade5ece1da092340afd300afe0387f207"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__v3__0.html#gade5ece1da092340afd300afe0387f207">XIICPS_CR_SLVMON_MASK</a>&#160;&#160;&#160;0x00000020U</td></tr>
<tr class="memdesc:gade5ece1da092340afd300afe0387f207"><td class="mdescLeft">&#160;</td><td class="mdescRight">Slave monitor mode.  <a href="group__iicps__v3__0.html#gade5ece1da092340afd300afe0387f207">More...</a><br /></td></tr>
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<tr class="memitem:ga11283b281c133a5b15d4da9ce99fa44e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__v3__0.html#ga11283b281c133a5b15d4da9ce99fa44e">XIICPS_CR_HOLD_MASK</a>&#160;&#160;&#160;0x00000010U</td></tr>
<tr class="memdesc:ga11283b281c133a5b15d4da9ce99fa44e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Hold bus 1=Hold scl, 0=terminate transfer.  <a href="group__iicps__v3__0.html#ga11283b281c133a5b15d4da9ce99fa44e">More...</a><br /></td></tr>
<tr class="separator:ga11283b281c133a5b15d4da9ce99fa44e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8eca5ebddd70579d4ecc3af1df21f4bf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__v3__0.html#ga8eca5ebddd70579d4ecc3af1df21f4bf">XIICPS_CR_ACKEN_MASK</a>&#160;&#160;&#160;0x00000008U</td></tr>
<tr class="memdesc:ga8eca5ebddd70579d4ecc3af1df21f4bf"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable TX of ACK when Master receiver.  <a href="group__iicps__v3__0.html#ga8eca5ebddd70579d4ecc3af1df21f4bf">More...</a><br /></td></tr>
<tr class="separator:ga8eca5ebddd70579d4ecc3af1df21f4bf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gada95425b2ab9cb404dcdc418d667370c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__v3__0.html#gada95425b2ab9cb404dcdc418d667370c">XIICPS_CR_NEA_MASK</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:gada95425b2ab9cb404dcdc418d667370c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Addressing Mode 1=7 bit, 0=10 bit.  <a href="group__iicps__v3__0.html#gada95425b2ab9cb404dcdc418d667370c">More...</a><br /></td></tr>
<tr class="separator:gada95425b2ab9cb404dcdc418d667370c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga77c04588069ca5f72be4e8177ff6c0d8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__v3__0.html#ga77c04588069ca5f72be4e8177ff6c0d8">XIICPS_CR_MS_MASK</a>&#160;&#160;&#160;0x00000002U</td></tr>
<tr class="memdesc:ga77c04588069ca5f72be4e8177ff6c0d8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Master mode bit 1=Master, 0=Slave.  <a href="group__iicps__v3__0.html#ga77c04588069ca5f72be4e8177ff6c0d8">More...</a><br /></td></tr>
<tr class="separator:ga77c04588069ca5f72be4e8177ff6c0d8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad8c3988f9bb22c7d3f2ce88f6a7f0aa0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__v3__0.html#gad8c3988f9bb22c7d3f2ce88f6a7f0aa0">XIICPS_CR_RD_WR_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:gad8c3988f9bb22c7d3f2ce88f6a7f0aa0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read or Write Master transfer 0=Transmitter, 1=Receiver.  <a href="group__iicps__v3__0.html#gad8c3988f9bb22c7d3f2ce88f6a7f0aa0">More...</a><br /></td></tr>
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<tr class="memitem:ga42b856fa59af3400a93291cf0e652307"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__v3__0.html#ga42b856fa59af3400a93291cf0e652307">XIICPS_CR_RESET_VALUE</a>&#160;&#160;&#160;0U</td></tr>
<tr class="memdesc:ga42b856fa59af3400a93291cf0e652307"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reset value of the Control register.  <a href="group__iicps__v3__0.html#ga42b856fa59af3400a93291cf0e652307">More...</a><br /></td></tr>
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<tr><td colspan="2"><div class="groupHeader">IIC Status Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register is used to indicate status of the IIC controller.</p>
<p>Read only </p>
</div></td></tr>
<tr class="memitem:ga67aa73d65f217cb22ecbbb10711ea561"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__v3__0.html#ga67aa73d65f217cb22ecbbb10711ea561">XIICPS_SR_BA_MASK</a>&#160;&#160;&#160;0x00000100U</td></tr>
<tr class="memdesc:ga67aa73d65f217cb22ecbbb10711ea561"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bus Active Mask.  <a href="group__iicps__v3__0.html#ga67aa73d65f217cb22ecbbb10711ea561">More...</a><br /></td></tr>
<tr class="separator:ga67aa73d65f217cb22ecbbb10711ea561"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae886bd15d96c8e3e3e8bbbcbc4878a5c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__v3__0.html#gae886bd15d96c8e3e3e8bbbcbc4878a5c">XIICPS_SR_RXOVF_MASK</a>&#160;&#160;&#160;0x00000080U</td></tr>
<tr class="memdesc:gae886bd15d96c8e3e3e8bbbcbc4878a5c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Receiver Overflow Mask.  <a href="group__iicps__v3__0.html#gae886bd15d96c8e3e3e8bbbcbc4878a5c">More...</a><br /></td></tr>
<tr class="separator:gae886bd15d96c8e3e3e8bbbcbc4878a5c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4ec47ab77103b89564d25650fee6132f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__v3__0.html#ga4ec47ab77103b89564d25650fee6132f">XIICPS_SR_TXDV_MASK</a>&#160;&#160;&#160;0x00000040U</td></tr>
<tr class="memdesc:ga4ec47ab77103b89564d25650fee6132f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transmit Data Valid Mask.  <a href="group__iicps__v3__0.html#ga4ec47ab77103b89564d25650fee6132f">More...</a><br /></td></tr>
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<tr class="memitem:gafbe8fcac03eab822b049d469485356d0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__v3__0.html#gafbe8fcac03eab822b049d469485356d0">XIICPS_SR_RXDV_MASK</a>&#160;&#160;&#160;0x00000020U</td></tr>
<tr class="memdesc:gafbe8fcac03eab822b049d469485356d0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Receiver Data Valid Mask.  <a href="group__iicps__v3__0.html#gafbe8fcac03eab822b049d469485356d0">More...</a><br /></td></tr>
<tr class="separator:gafbe8fcac03eab822b049d469485356d0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga694b3781a9539f3c34b97a4d58b68efd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__v3__0.html#ga694b3781a9539f3c34b97a4d58b68efd">XIICPS_SR_RXRW_MASK</a>&#160;&#160;&#160;0x00000008U</td></tr>
<tr class="memdesc:ga694b3781a9539f3c34b97a4d58b68efd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Receive read/write Mask.  <a href="group__iicps__v3__0.html#ga694b3781a9539f3c34b97a4d58b68efd">More...</a><br /></td></tr>
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<tr><td colspan="2"><div class="groupHeader">IIC Address Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Normal addressing mode uses add[6:0].</p>
<p>Extended addressing mode uses add[9:0]. A write access to this register always initiates a transfer if the IIC is in master mode. Read/Write </p>
</div></td></tr>
<tr class="memitem:ga65d613d28fe2707d6e1d0fb2ea5b0d9e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__v3__0.html#ga65d613d28fe2707d6e1d0fb2ea5b0d9e">XIICPS_ADDR_MASK</a>&#160;&#160;&#160;0x000003FF</td></tr>
<tr class="memdesc:ga65d613d28fe2707d6e1d0fb2ea5b0d9e"><td class="mdescLeft">&#160;</td><td class="mdescRight">IIC Address Mask.  <a href="group__iicps__v3__0.html#ga65d613d28fe2707d6e1d0fb2ea5b0d9e">More...</a><br /></td></tr>
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<tr><td colspan="2"><div class="groupHeader">IIC Data Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>When written to, the data register sets data to transmit.</p>
<p>When read from, the data register reads the last received byte of data. Read/Write </p>
</div></td></tr>
<tr class="memitem:ga324b3ca19000b5cc8944daf85c8f7736"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__v3__0.html#ga324b3ca19000b5cc8944daf85c8f7736">XIICPS_DATA_MASK</a>&#160;&#160;&#160;0x000000FF</td></tr>
<tr class="memdesc:ga324b3ca19000b5cc8944daf85c8f7736"><td class="mdescLeft">&#160;</td><td class="mdescRight">IIC Data Mask.  <a href="group__iicps__v3__0.html#ga324b3ca19000b5cc8944daf85c8f7736">More...</a><br /></td></tr>
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<tr><td colspan="2"><div class="groupHeader">IIC Interrupt Registers</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p><b>IIC Interrupt Status Register</b></p>
<p>This register holds the interrupt status flags for the IIC controller. Some of the flags are level triggered</p><ul>
<li>i.e. are set as long as the interrupt condition exists. Other flags are edge triggered, which means they are set one the interrupt condition occurs then remain set until they are cleared by software. The interrupts are cleared by writing a one to the interrupt bit position in the Interrupt Status Register. Read/Write.</li>
</ul>
<p><b>IIC Interrupt Enable Register</b></p>
<p>This register is used to enable interrupt sources for the IIC controller. Writing a '1' to a bit in this register clears the corresponding bit in the IIC Interrupt Mask register. Write only.</p>
<p><b>IIC Interrupt Disable Register </b></p>
<p>This register is used to disable interrupt sources for the IIC controller. Writing a '1' to a bit in this register sets the corresponding bit in the IIC Interrupt Mask register. Write only.</p>
<p><b>IIC Interrupt Mask Register</b></p>
<p>This register shows the enabled/disabled status of each IIC controller interrupt source. A bit set to 1 will ignore the corresponding interrupt in the status register. A bit set to 0 means the interrupt is enabled. All mask bits are set and all interrupts are disabled after reset. Read only.</p>
<p>All four registers have the same bit definitions. They are only defined once for each of the Interrupt Enable Register, Interrupt Disable Register, Interrupt Mask Register, and Interrupt Status Register </p>
</div></td></tr>
<tr class="memitem:ga88441aea66e1ef8f1fd211756b1d1630"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__v3__0.html#ga88441aea66e1ef8f1fd211756b1d1630">XIICPS_IXR_ARB_LOST_MASK</a>&#160;&#160;&#160;0x00000200U</td></tr>
<tr class="memdesc:ga88441aea66e1ef8f1fd211756b1d1630"><td class="mdescLeft">&#160;</td><td class="mdescRight">Arbitration Lost Interrupt mask.  <a href="group__iicps__v3__0.html#ga88441aea66e1ef8f1fd211756b1d1630">More...</a><br /></td></tr>
<tr class="separator:ga88441aea66e1ef8f1fd211756b1d1630"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6b92f85baedcc73892a141f80afe3462"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__v3__0.html#ga6b92f85baedcc73892a141f80afe3462">XIICPS_IXR_RX_UNF_MASK</a>&#160;&#160;&#160;0x00000080U</td></tr>
<tr class="memdesc:ga6b92f85baedcc73892a141f80afe3462"><td class="mdescLeft">&#160;</td><td class="mdescRight">FIFO Recieve Underflow Interrupt mask.  <a href="group__iicps__v3__0.html#ga6b92f85baedcc73892a141f80afe3462">More...</a><br /></td></tr>
<tr class="separator:ga6b92f85baedcc73892a141f80afe3462"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad2473caf4558fac9af1bd071a022e3cf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__v3__0.html#gad2473caf4558fac9af1bd071a022e3cf">XIICPS_IXR_TX_OVR_MASK</a>&#160;&#160;&#160;0x00000040U</td></tr>
<tr class="memdesc:gad2473caf4558fac9af1bd071a022e3cf"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transmit Overflow Interrupt mask.  <a href="group__iicps__v3__0.html#gad2473caf4558fac9af1bd071a022e3cf">More...</a><br /></td></tr>
<tr class="separator:gad2473caf4558fac9af1bd071a022e3cf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1f69893ddec793ff77b61deb51665aa5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__v3__0.html#ga1f69893ddec793ff77b61deb51665aa5">XIICPS_IXR_RX_OVR_MASK</a>&#160;&#160;&#160;0x00000020U</td></tr>
<tr class="memdesc:ga1f69893ddec793ff77b61deb51665aa5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Receive Overflow Interrupt mask.  <a href="group__iicps__v3__0.html#ga1f69893ddec793ff77b61deb51665aa5">More...</a><br /></td></tr>
<tr class="separator:ga1f69893ddec793ff77b61deb51665aa5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5c873e7df9f7a05e458b0d7e9b50faa9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__v3__0.html#ga5c873e7df9f7a05e458b0d7e9b50faa9">XIICPS_IXR_SLV_RDY_MASK</a>&#160;&#160;&#160;0x00000010U</td></tr>
<tr class="memdesc:ga5c873e7df9f7a05e458b0d7e9b50faa9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Monitored Slave Ready Interrupt mask.  <a href="group__iicps__v3__0.html#ga5c873e7df9f7a05e458b0d7e9b50faa9">More...</a><br /></td></tr>
<tr class="separator:ga5c873e7df9f7a05e458b0d7e9b50faa9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6df84833528a63b5f5fb07a7d1743c91"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__v3__0.html#ga6df84833528a63b5f5fb07a7d1743c91">XIICPS_IXR_TO_MASK</a>&#160;&#160;&#160;0x00000008U</td></tr>
<tr class="memdesc:ga6df84833528a63b5f5fb07a7d1743c91"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transfer Time Out Interrupt mask.  <a href="group__iicps__v3__0.html#ga6df84833528a63b5f5fb07a7d1743c91">More...</a><br /></td></tr>
<tr class="separator:ga6df84833528a63b5f5fb07a7d1743c91"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga74650276000c8cc48cce610b8c6d2140"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__v3__0.html#ga74650276000c8cc48cce610b8c6d2140">XIICPS_IXR_NACK_MASK</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:ga74650276000c8cc48cce610b8c6d2140"><td class="mdescLeft">&#160;</td><td class="mdescRight">NACK Interrupt mask.  <a href="group__iicps__v3__0.html#ga74650276000c8cc48cce610b8c6d2140">More...</a><br /></td></tr>
<tr class="separator:ga74650276000c8cc48cce610b8c6d2140"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa4e9c302ebb54b53aa67ec6c9f4616a3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__v3__0.html#gaa4e9c302ebb54b53aa67ec6c9f4616a3">XIICPS_IXR_DATA_MASK</a>&#160;&#160;&#160;0x00000002U</td></tr>
<tr class="memdesc:gaa4e9c302ebb54b53aa67ec6c9f4616a3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data Interrupt mask.  <a href="group__iicps__v3__0.html#gaa4e9c302ebb54b53aa67ec6c9f4616a3">More...</a><br /></td></tr>
<tr class="separator:gaa4e9c302ebb54b53aa67ec6c9f4616a3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga56fefd834bba9cc03c0a84bd2a3e099a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__v3__0.html#ga56fefd834bba9cc03c0a84bd2a3e099a">XIICPS_IXR_COMP_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:ga56fefd834bba9cc03c0a84bd2a3e099a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transfer Complete Interrupt mask.  <a href="group__iicps__v3__0.html#ga56fefd834bba9cc03c0a84bd2a3e099a">More...</a><br /></td></tr>
<tr class="separator:ga56fefd834bba9cc03c0a84bd2a3e099a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga98fd97807996f571433d9235dc0b0ca4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__v3__0.html#ga98fd97807996f571433d9235dc0b0ca4">XIICPS_IXR_DEFAULT_MASK</a>&#160;&#160;&#160;0x000002FFU</td></tr>
<tr class="memdesc:ga98fd97807996f571433d9235dc0b0ca4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Default ISR Mask.  <a href="group__iicps__v3__0.html#ga98fd97807996f571433d9235dc0b0ca4">More...</a><br /></td></tr>
<tr class="separator:ga98fd97807996f571433d9235dc0b0ca4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8e324637da3483d518d499b7257c7631"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__v3__0.html#ga8e324637da3483d518d499b7257c7631">XIICPS_IXR_ALL_INTR_MASK</a>&#160;&#160;&#160;0x000002FFU</td></tr>
<tr class="memdesc:ga8e324637da3483d518d499b7257c7631"><td class="mdescLeft">&#160;</td><td class="mdescRight">All ISR Mask.  <a href="group__iicps__v3__0.html#ga8e324637da3483d518d499b7257c7631">More...</a><br /></td></tr>
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<tr><td colspan="2"><div class="groupHeader">IIC Transfer Size Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>The register's meaning varies according to the operating mode as follows:</p>
<ul>
<li>Master transmitter mode: number of data bytes still not transmitted minus one</li>
<li>Master receiver mode: number of data bytes that are still expected to be received</li>
<li>Slave transmitter mode: number of bytes remaining in the FIFO after the master terminates the transfer</li>
<li>Slave receiver mode: number of valid data bytes in the FIFO</li>
</ul>
<p>This register is cleared if CLR_FIFO bit in the control register is set. Read/Write </p>
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<tr class="memitem:ga15b4866837028af069caa628b3a855c2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__v3__0.html#ga15b4866837028af069caa628b3a855c2">XIICPS_TRANS_SIZE_MASK</a>&#160;&#160;&#160;0x0000003F</td></tr>
<tr class="memdesc:ga15b4866837028af069caa628b3a855c2"><td class="mdescLeft">&#160;</td><td class="mdescRight">IIC Transfer Size Mask.  <a href="group__iicps__v3__0.html#ga15b4866837028af069caa628b3a855c2">More...</a><br /></td></tr>
<tr class="separator:ga15b4866837028af069caa628b3a855c2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga609b88168d4a0681b42005e0d402a7eb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__v3__0.html#ga609b88168d4a0681b42005e0d402a7eb">XIICPS_FIFO_DEPTH</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:ga609b88168d4a0681b42005e0d402a7eb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Number of bytes in the FIFO.  <a href="group__iicps__v3__0.html#ga609b88168d4a0681b42005e0d402a7eb">More...</a><br /></td></tr>
<tr class="separator:ga609b88168d4a0681b42005e0d402a7eb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaaf1867a207f808f18a373435dee8f525"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__v3__0.html#gaaf1867a207f808f18a373435dee8f525">XIICPS_DATA_INTR_DEPTH</a>&#160;&#160;&#160;14</td></tr>
<tr class="memdesc:gaaf1867a207f808f18a373435dee8f525"><td class="mdescLeft">&#160;</td><td class="mdescRight">Number of bytes at DATA intr.  <a href="group__iicps__v3__0.html#gaaf1867a207f808f18a373435dee8f525">More...</a><br /></td></tr>
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<tr><td colspan="2"><div class="groupHeader">IIC Slave Monitor Pause Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register is associated with the slave monitor mode of the I2C interface.</p>
<p>It is meaningful only when the module is in master mode and bit SLVMON in the control register is set.</p>
<p>This register defines the pause interval between consecutive attempts to address the slave once a write to an I2C address register is done by the host. It represents the number of sclk cycles minus one between two attempts.</p>
<p>The reset value of the register is 0, which results in the master repeatedly trying to access the slave immediately after unsuccessful attempt. Read/Write </p>
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<tr class="memitem:ga6bc4423ced1691dc807ed57ddf4d2a97"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__v3__0.html#ga6bc4423ced1691dc807ed57ddf4d2a97">XIICPS_SLV_PAUSE_MASK</a>&#160;&#160;&#160;0x0000000F</td></tr>
<tr class="memdesc:ga6bc4423ced1691dc807ed57ddf4d2a97"><td class="mdescLeft">&#160;</td><td class="mdescRight">Slave monitor pause mask.  <a href="group__iicps__v3__0.html#ga6bc4423ced1691dc807ed57ddf4d2a97">More...</a><br /></td></tr>
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<tr><td colspan="2"><div class="groupHeader">IIC Time Out Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>The value of time out register represents the time out interval in number of sclk cycles minus one.</p>
<p>When the accessed slave holds the sclk line low for longer than the time out period, thus prohibiting the I2C interface in master mode to complete the current transfer, an interrupt is generated and TO interrupt flag is set.</p>
<p>The reset value of the register is 0x1f. Read/Write </p>
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<tr class="memitem:ga5816d28492ddffba63659c197da00ed2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__v3__0.html#ga5816d28492ddffba63659c197da00ed2">XIICPS_TIME_OUT_MASK</a>&#160;&#160;&#160;0x000000FFU</td></tr>
<tr class="memdesc:ga5816d28492ddffba63659c197da00ed2"><td class="mdescLeft">&#160;</td><td class="mdescRight">IIC Time Out mask.  <a href="group__iicps__v3__0.html#ga5816d28492ddffba63659c197da00ed2">More...</a><br /></td></tr>
<tr class="separator:ga5816d28492ddffba63659c197da00ed2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafbad4feee5924c925b1fe0d864c3799a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__v3__0.html#gafbad4feee5924c925b1fe0d864c3799a">XIICPS_TO_RESET_VALUE</a>&#160;&#160;&#160;0x000000FFU</td></tr>
<tr class="memdesc:gafbad4feee5924c925b1fe0d864c3799a"><td class="mdescLeft">&#160;</td><td class="mdescRight">IIC Time Out reset value.  <a href="group__iicps__v3__0.html#gafbad4feee5924c925b1fe0d864c3799a">More...</a><br /></td></tr>
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</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
Functions</h2></td></tr>
<tr class="memitem:gabfedbe03a6ac7de3d4e0ac192b8ab288"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__v3__0.html#gabfedbe03a6ac7de3d4e0ac192b8ab288">XIicPs_ResetHw</a> (u32 BaseAddress)</td></tr>
<tr class="memdesc:gabfedbe03a6ac7de3d4e0ac192b8ab288"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function perform the reset sequence to the given I2c interface by configuring the appropriate control bits in the I2c specifc registers the i2cps reset squence involves the following steps Disable all the interuupts Clear the status Clear FIFO's and disable hold bit Clear the line status Update relevant config registers with reset values.  <a href="group__iicps__v3__0.html#gabfedbe03a6ac7de3d4e0ac192b8ab288">More...</a><br /></td></tr>
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